Even/odd byte lanes and N-way interleaving
A two-lane byte split of 00 01 02 03 04 05 produces lane 0 00 02 04 and lane 1 01 03 05. Four byte lanes extract every fourth byte. With two lanes of two bytes, 00 01 02 03 04 05 06 07 becomes 00 01 04 05 and 02 03 06 07.
Interleave reconstructs these groups. Concatenate joins one complete selected file window after another; it does not alternate lanes. The lane permutation ties displayed file slots to logical lane positions, and input arrows make order explicit.
Byte swapping, source offsets and EPROM padding
Swap byte pairs to reverse each 16-bit unit. Reverse four bytes to change each 32-bit unit's byte order. Swap 16-bit words to exchange the two halves of each four-byte unit while keeping each pair intact. Swaps start at offset zero of the selected or merged data, as shown in the report pipeline.
Chip capacity in bits is eight times the file size in bytes: a 27C256 stores 32,768 bytes; a 27C512 stores 65,536 bytes. Enter the required output size in bytes and select the fill value your programmer expects. The output placement offset is a byte offset in the generated file, not a CPU address or programmer address.
Supported operations and verification boundaries
Version 1 handles raw binary files, 2–8 lanes of 1/2/4 bytes, concatenation, source windows, the three explicit swaps, placement/fill and whole-file checksums. It rejects empty inputs, out-of-range windows, incomplete groups, unequal interleave lanes and output overflow. It preserves input files and performs no device programming.
It does not infer bus endianness, chip socket order, address-line permutations, proprietary ROM headers, game checksums, mirrored banks or device-specific checksum corrections. Confirm exact sizes, wiring and byte order against the board and programmer documentation, then verify programmed readback against the generated image. Hash agreement establishes file identity; it does not establish correct board mapping.
Frequently asked questions
How are even and odd bytes split?
With two lanes of one byte each and lane order 0,1, slot 0 receives bytes at selected offsets 0,2,4… and slot 1 receives 1,3,5…. These offsets start at the selected source window, not necessarily the beginning of the original file.
Does lane 0 mean the high or low ROM chip?
No. Lane numbers describe byte positions within each source group. High/low chip names depend on the CPU, bus wiring, dump format and programmer. Check the board documentation before choosing an order.
Can I merge split images back into the original?
Yes. Interleave the unpadded split outputs in the same slot order with the same lane count, width and lane permutation. Remove output fill with the source window first if you added padding. Swaps and cropping must also be reversed explicitly.
What do output size and placement offset do?
The placement offset adds fill bytes before the payload. Output size is the total size of each downloaded image, including prefix and suffix fill. A blank size uses the minimum required size. Undersized targets and incomplete groups are rejected rather than truncated.
Which EPROM checksums are supported?
CRC32 ISO-HDLC, SHA-1, SHA-256, the sum of bytes modulo 256 and the sum of bytes modulo 65536. All cover complete downloaded images including fill. These are not board-specific word checksums or checksum repairs.
Are binary images uploaded?
No. Reading, transforms and hashing run locally with a cancellable worker. Important file names, hex previews, hash comparison text and derived report data are masked for Clarity.
Primary references
The One ROM image-transform documentation describes lane stride, width and byte swapping. The splitrom project illustrates bank and chip ordering for Atari ROMs. RFC 1952 includes the reflected CRC32 algorithm, and the Web Cryptography API defines digest operations.